1. Field of the Invention
The present invention relates to a multi-layer circuit board for mounting an electronic part such as a semiconductor chip or a semiconductor device having a number of electrodes, pads, or lands, hereinafter referred to as lands, arranged in a lattice form or in a staggered form.
2. Description of the Related Art
In modern semiconductor devices, the logic devices are becoming highly functional and highly integrated, feature more inputs and outputs, and are being mounted ever more densely. Therefore, products have been produced to compensate for a lack of space for forming lands, and to cope with increased numbers of inputs and outputs, by arranging lands like an array on the land-forming surface of a semiconductor chip. FIG. 25 illustrates a prior art or mounting a semiconductor chip 4 on a substrate 5 relying on a flip chip connection. The semiconductor chip 4 shown here has lands 6 arranged on the outer peripheral edges thereof. Circuit patterns 7 are connected to the, lands 6 and are drawn outwardly. In this case the respective circuit patterns 7 are connected to the respective electrodes 6 on a single, common surface.
FIG. 24 illustrates the arrangement of lands on a wiring member for mounting a semiconductor chip having two rows of lands 6 arranged along the outer peripheral edges of the land-forming surface, and the arrangement of circuit patterns 7 connected to the lands 8. In this example, the pattern 7 is drawn from an intermediate portion of the space between the adjacent two lands 8; i.e., the respective circuit pattern 7 is drawn from the respective land 8 on a single common surface. In drawing the circuit patterns 7 from the lands 8 arranged in plural rows, it is general practice to connect a pattern on the land 8 of the inner side and to draw the pattern outwardly through the intermediate portion between the two adjacent lands 8 of the outer side.
When a number of lands are arranged like an array on the land-forming surface to increase the numbers of inputs and outputs, however, it becomes no longer possible to draw the wirings toward the outer side from all lands on the surface though it may vary depending upon the distance between the lands and the number of the lands.
To solve this problem, it has been contrived to form circuit boards in many layers for mounting a semiconductor chip, and to suitably arrange the circuit patterns on the laminated circuit boards, in order to electrically connect the lands to every land of the semiconductor chip and to make the circuit patterns. FIG. 26 illustrates an example where a semiconductor chip 4 is mounted on a multi-layer circuit board obtained by laminating a plurality of layers. Thus, according to the method of laminating the plurality of layers, it becomes possible to electrically connect the semiconductor chip 4 having a number of lands 6 arranged like an array to the external connection terminals without causing the circuit patterns to interfere. In FIG. 26, reference numeral 7a denotes a circuit pattern of an inner layer, and 5a to 5d denote circuit boards which are the first to fourth layers.
When the semiconductor chip having lands arranged like an array is to be mounted on the circuit board, about two circuit boards may be laminated one upon the other provided the number of the lands is not very large. When the semiconductor chip has as many pins as, for example, 30xc3x9730 pins or 40xc3x9740 pins, however, the circuit boards must be laminated in 6 to 10 layers.
When the circuit boards in which the circuit patterns are very densely formed are to be laminated in many layers, there will be employed a high-density wiring method such as build-up method accompanied, however, by serious problems in regard to yield of the products, reliability and the cost of production. That is, when the circuit patterns are to be formed in many layers, vias are formed in each layer to accomplish an electric connection between the circuit patterns and the circuit patterns across the layer, and the layers are successively laminated, requiring a high degree of precision without, however, offering high degree of reliability. When many layers are laminated, furthermore, it is required that none of the layers is defective, involving further increased technical difficulty.
To produce a multi-layer circuit board by laminating circuit patterns in many layers, while maintaining a good yield, a reduction in the number of wiring layers could be an effective solution.
The present invention is concerned with a multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many as 40xc3x9740 pins arranged in an array on the side of the mounting surface or a semiconductor device having lands arranged in an array on the side of the mounting surface. The object of the present invention is to provide a multi-layer circuit board which makes it possible to mount an electronic part such as a semiconductor chip or a semiconductor device, despite a decreased number of circuit boards being laminated one upon the other, which features improved yield of production and which can be used as a highly reliable product. In order to accomplish the above-mentioned object, the present invention provides the following multi-layer circuit board.
The present invention provides a multi-layer circuit board formed by e.g., laminating a plurality of layers in order to mount an electronic part such as a semiconductor chip or a semiconductor device having many lands arranged in the form of an array. Upon contriving the arrangement of circuit patterns on each circuit layer, a multi-layer circuit board can be constituted by forming the circuit boards (wiring layers) in a decreased number of layers. There is no particular limitation on the method of fabricating the multi-layer circuit board, and various methods, such as a build-up method, can be employed.
Arrangements of lands of the electronic parts can be divided into a normal lattice arrangement and a staggered lattice arrangement. Here, when the lands are arranged in the normal lattice form or staggered lattice form, a problem arises in regard to how the circuit patterns can be arranged to accomplish the highest efficiency.
The circuit patterns pass through among the lands. In the practical products, therefore, the circuit patterns must be set depending upon the predetermined conditions such as pitch of lands, diameter of lands, width of patterns and gap between the patterns.
According to the present invention, the following method is employed for determining the arrangement of circuit patterns on each circuit board in a multi-layer circuit board formed by laminating the circuit boards. Upon arranging the circuit patterns according to this method, it is possible to form a multi-layer circuit board in the least number of layers.
First, considered below is a case where the lands are formed in a normal lattice arrangement maintaining an equal distance in the vertical and lateral directions.
Let it now be presumed that intermediate lands of a number of (nxe2x88x922) do not exist except for the lands at both ends in the arrangement of lands of a number of n maintaining an equal distance, and that the number of wirings that can be passed (arranged) among the lands between both ends except the lands at both ends is m, then, m is given by the following formula,                     m        =                  xe2x80x83                ⁢                  {                                                    (                                  land                  ⁢                                      xe2x80x83                                    ⁢                  pitch                                )                            xc3x97                              (                                  n                  -                  1                                )                                      -                          (                              land                ⁢                                  xe2x80x83                                ⁢                diameter                            )                        -                                                                        xe2x80x83                    ⁢                      (                          space              ⁢                              xe2x80x83                            ⁢              between              ⁢                              xe2x80x83                            ⁢              patterns                        )                    }                +                                          xe2x80x83                ⁢                  (                                    pattern              ⁢                              xe2x80x83                            ⁢              width                        +                          space              ⁢                              xe2x80x83                            ⁢              between              ⁢                              xe2x80x83                            ⁢              patterns                                )                    
where land pitch is a distance between the centers of the lands (xe2x80x9caxe2x80x9d in FIG. 1), land diameter is a diameter of the land (xe2x80x9cbxe2x80x9d in FIG. 1), space between patterns is a minimum distance that must be maintained between the neighboring circuit patterns (xe2x80x9ccxe2x80x9d in FIG. 1), and the pattern width is xe2x80x9cdxe2x80x9d in FIG. 1.
If it is considered that only one circuit pattern is allowed to pass through between the neighboring lands that are arranged in a number of n maintaining an equal distance, then, the number k of circuit patterns that can be arranged among the lands between the two ends is given by,
k=(nxe2x88x921)+(nxe2x88x922)=2nxe2x88x923
This means that there are (nxe2x88x921) channels that permit the passage of circuit patterns among the lands of a number of n, that there are intermediate lands of a number of (nxe2x88x922) excluding the lands at both ends, and that a circuit pattern can be drawn from each of these lands.
Upon comparing m with (k+1), therefore, when m less than (k+1), there is obtained no effect for increasing the circuit patterns even if the circuit patterns are so arranged as to remove all intermediate lands among the lands of a number of n. When mxe2x89xa7(k+1), there is obtained the effect for increasing the circuit patterns when the circuit patterns are so arranged as to remove the intermediate lands.
In order to constitute a multi-layer circuit board using circuit boards in as small a number as possible, therefore, a minimum integer that gives mxe2x89xa7(k+1) is selected as a parameter, and the circuit patterns are arranged according to the value n.
Then, a value m is found from the conditions of a given land pitch, land diameter and pattern width, and is compared with (k+1) to find a minimum value n (integer) that gives mxe2x89xa7(k+1). Then, the conditions are found that remove the land sequences of a number of (nxe2x88x922) for the value n, and the circuit patterns are preferentially drawn from the land sequences of the number of (nxe2x88x922) to accomplish an optimum arrangement.
FIG. 1 illustrates an example in which the circuit patterns are effectively increased with n=3 to accomplish an efficient arrangement. In FIG. 1, the distance Lxe2x80x94L represents two land pitches. When the lands 10 exist between the distance Lxe2x80x94L, three circuit patterns can be arranged, i.e., a circuit pattern drawn from an intermediate land and two circuit patterns passing through the two lands sandwiched by the lands on both sides and the intermediate land.
On the other hand, when a land is removed between the distance Lxe2x80x94L, and a circuit pattern is passed through a portion where the land used to exist, there can be arranged four circuit patterns between the distance Lxe2x80x94L as shown. That is, among the three lands, an intermediate land is removed, and a circuit pattern 7 is passed to increase the number of circuit patterns by one. From this, every other land is erased from the land sequences, i.e., the circuit pattern is preferentially drawn from the land of an intermediate sequence, in order to increase the number of circuit patterns that are drawn out and to accomplish an efficient arrangement.
In the object product, the land pitch, land diameter, pattern width and space between patterns have been determined in advance, and it is easy to find the values m and (k+1) based on these values with n as a parameter. Based upon the calculated results, it can be easily determined which arrangement of circuit patterns would be efficient.
As will be described later by way of Examples, the circuit patterns on each circuit layer are designed by commonly setting the positions of land sequences (that are to be removed) from where the circuit patterns are to be drawn on each of the layers, and for the land sequences from where the circuit patterns are drawn on the preceding layer, the circuit patterns are also drawn from the same land sequences even on the next layer.
The foregoing description has dealt with the case where only one circuit pattern could be passed through between the neighboring lands. However, the same idea holds true even when the circuit patterns of a number of a can be passed through between the neighboring lands maintaining an ordinary distance.
Even in this case, when the (nxe2x88x922) intermediate lands do not exist in the arrangement of the (n) lands maintaining an equal distance, the number m of circuit patterns that can be passed between the lands at both ends is given by,                     m        =                  xe2x80x83                ⁢                  {                                                    (                                  land                  ⁢                                      xe2x80x83                                    ⁢                  pitch                                )                            xc3x97                              (                                  n                  -                  1                                )                                      -                          (                              land                ⁢                                  xe2x80x83                                ⁢                diameter                            )                        -                                                                        xe2x80x83                    ⁢                      (                          space              ⁢                              xe2x80x83                            ⁢              between              ⁢                              xe2x80x83                            ⁢              patterns                        )                    )                .        +                                          xe2x80x83                ⁢                  (                                    pattern              ⁢                              xe2x80x83                            ⁢              width                        +                          space              ⁢                              xe2x80x83                            ⁢              between              ⁢                              xe2x80x83                            ⁢              patterns                                )                    
When the intermediate lands are not erased, the number of circuit patterns that can be arranged among the lands of the number of n between the two ends is given by,
k=xcex1(nxe2x88x921)+(nxe2x88x922)
Therefore, the values m and (k+1) found with n as a parameter are compared with each other to determine a minimum value n (integer) that gives mxe2x89xa7(k+1), conditions are determined based on the number of n for selectively subtracting the circuit patterns from the land sequences of the number of (nxe2x88x922), and the land sequences are erased depending upon the conditions, in order to efficiently design the circuit patterns. That is, the idea for arranging a single circuit pattern can be adapted even under the condition where a plurality of circuit patterns are arranged between the neighboring lands (in the channel portion), in order to efficiently design the circuit patterns.
When the (nxe2x88x922) lands are to be selected from the consecutively arranged (n) lands, the lands to be selected are those lands that remain when the lands at both ends are removed from the lands of the number of n.
Which (nxe2x88x922) lands should be selected from the land sequences arranged in plural sequences or, in other words, how the (nxe2x88x922) lands be arranged, is determined depending upon the case where the consecutively arranged lands of the number of n are repetitively arranged in a manner that the last land is overlapped on the first land of the next lands of the number of n (in this case, the sequences of the number of (nxe2x88x921) serve as a recurring unit), depending upon the case where the lands of the number of n are repetitively arranged in a manner that the last land is positioned neighboring the first land of the next lands of the number of n (in this case, the sequences of the number of n serve as a recurring unit), and depending upon the case where the lands of the number of n are repetitively arranged in a manner that one or more additional lands are interposed between the last land and the first land of the next lands of the number of n.
The method of arranging the circuit patterns adapted to the above-mentioned case of normal lattice arrangement can be adapted, too, to the case where the lands are arranged in the staggered lattice form. That is, the staggered lattice arrangement can be regarded to be a lattice arrangement when viewed from a diagonal direction. Therefore, this arrangement is regarded to be the lattice arrangement as viewed from the diagonal direction, and there can be adapted the same as the lattice arrangement. That is, when the lattice arrangement is regarded to be the one that is viewed from the diagonal direction, values m and (k+1) are found from the land pitch, land diameter, pattern width, and space between patterns using n as a parameter, and an effective value n is found therefrom, and the land sequences are determined depending upon the value n for preferentially drawing the circuit patterns based on the same idea as that of the case of the lattice arrangement. In the case of the normal lattice arrangement, the method of the present invention can be effectively adapted to the case where it is possible to pass only one circuit pattern between the neighboring lands and the land arrangement is not smaller than 6xc3x976. In a normal semiconductor chip, furthermore, the lands are arranged according to the normal lattice arrangement or the normal staggered lattice arrangement while maintaining an equal distance in the vertical and lateral directions. However, the idea of the present invention can be adapted even to a semiconductor chip having pitches of arrangements that are slightly different in the vertical and lateral directions.